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RTL verification

RTL verification

“Science may set limits to knowledge, but you should not set limits to imagination”
~Bertrand Russel

IEEE IA/IE/PELS Jt. Chapter Kerala and IEEE Comsoc Kerala Chapter together brings you the second workshop for the 3-Day Technical Conclave, Indicomm on the topic RTL Verification.

Speaker:
Dr. Jayaraj U Kidav, Scientist ‘D’ at NIELIT Calicut.

Date : 10th October, 2021

Who can attend?
The registration is open to all professional members, research scholars, Mtech and Btech students.

Buckle up and join us on this journey to unravel the amazing world of electronics!

Register at: https://www.yepdesk.com/indicomm

All those who have already registered for ASIC and FPGA Design Flow, need not register again 🙂

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